Created it, 06/09/09
Update it, 06/09/25
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In this theory, we will examine the following combinative circuits: adders, comparators, multiplexers and demultiplexers.
1. - ADDERS
1. 1. - ADDITION OF TWO BINARY DIGITS
In the binary system, one can represent any number as in the decimal system and one can carry out the four elementary arithmetic operations : addition, subtraction, multiplication and division.
Like let us know we it, the three last operations can all be brought back to the addition which is thus most important.
We first of all will point out the addition of two binary numbers of 1 bit, we obtain the 4 following sums :
0 + 0 = 0
0 + 1 = 1
1 + 0 = 1
1 + 1 = 10
1st case : the two figures are 0 and it sum is 0.
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2nd and 3rd case : a figure is worth 0, the other is worth 1 : the sum is worth 1.
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4th case : The two figures are worth 1 and the sum is worth 10 (= 210).
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It is noticed that in the first three cases, it is enough to only one binary digit (or bit) to indicate the result. In the fourth case, one needs two digits : that located on the right is the result (here 0) and the other is reserve (here 1).
The described procedure is the same one as for the addition in the decimal system. It differs only by the quantity from figures brought into play : two binary digits against the ten decimal ones.
Figure 1 shows the additions of the figures 0 and 1 relating to the two systems.
We notice that the results are the same ones, although in the binary system it is necessary to take account of reserve to express the result two.
1. 2. - CIRCUIT SUMMER
Since we know the rules of the binary addition, we will see now how this operation can be carried out by logical circuits.
It is necessary to carry out a combinative circuit (figure 2) whose two entries A and B and the exits S and C answer the truth table of figure 1.
It is noticed that S is with state 1 if only one of the entries is with state 1.
We thus have business with the switching function OR Exclusive, that is to say :
S = A
B
In addition, it is noticed that C is with state 1 only if A and B are with state 1.
One thus deduces from it that :
C = A . B
The circuit which carries out the sum of two bits can be obtained by associating a door OR Exclusive and a door AND as shown in the figure 3.
1. 3. - ADDITION OF BINARY NUMBERS OF SEVERAL FIGURES
The circuit summer examined previously is able to add between them two binary numbers of only one figure. For this reason, it is called half-adder.
Indeed, when one must add with the numbers of more than one figure, it becomes necessary to have circuits which take account of the reserve of the sum carried out on the figures of immediately lower row.
To include/understand that, we will examine how one carries out the addition of two decimal numbers, for example :
This operation is carried out by successive stages : one adds initially the figures with right-hand side, then the following by adding possible reserve.
Initially, one makes the addition of 4 and 8 whose sum is 12 ; one writes result 2 and one retains 1.
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In the following stage, one must make an addition of 3 digits because one must take account of reserve (here 1). The sum of 7 and 5 plus reserve 1, gives 13 ; one thus writes 3 and one retains 1.
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The last stage is similar to the preceding one : sum 8 is however without reserve.
The same procedure also applies to the binary numbers.
It is thus necessary to carry out a circuit which can add the two of the same figures row with a binary number with reserve of the preceding stage, that is to say three binary digits.
The full adder thus has three entries, two for the terms and for reserve.
That is to say to carry out the sum of the two binary numbers of 8 following bits :
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What gives in decimal code :
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One leaves the last position on the right, where two are 1. One carries out the sum of these two figures according to the table of figure 1, which gives like result 0 and reserve 1.
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With the following stage, one must add 3 digits whereas the table of figure 1 is limited to the sum of 2 digits.
We thus will build a table indicating the sum of 3 digits.
With 3 digits, there are 8 possibilities which go from 0 + 0 + 0 to 1 + 1 + 1.
For each one of these possibilities, it is easy to raise the sum.
For example :
0 + 0 + 0 = 0 (result 0, retained 0)
0 + 1 + 1 = 210 = 10 (result 0, retained 1)
1 + 1 + 1 = 310 = 11 (result 1, retained 1).
The table of figure 4 summarizes all the possible combinations.
In this table, Ai and Bi are the terms of row : Ci is reserve relating to the sum of Ai and Bi ; Ci + 1 is reserve relating to the sum of Ai, Bi and Ci. Si is the result of the sum Ai, Bi and Ci.
Let us return now to the sum taken in example; by using the table of figure 4, one obtains for the terms of row 2 :
1 + 0 + 0 = 1 with a reserve equalizes to 0.
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If one adds the following figures, one a :
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And so on until the final result :
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Let us check the result :
11010110 = (1 x 128) + (1 x 64) + (0 x 32) + (1 x 16) + (0 x 8) + (1 x 4) + (1 x 2) + (0 x 1) = 128 + 64 + 16 + 4 + 2 = 214.
1. 4. - COMPLETE
CIRCUIT SUMMER
It is thus necessary to carry out a circuit which corresponds to the truth table of figure 4, one obtains the diagram of figure 5 which represents a full adder.
Let us seek now the equation of Ci + 1 and Si by using the table of figure 4.
For that, let us draw the corresponding pictures of Karnaugh deferred on figure 6.
First table of Karnaugh, one draws the equation from Si following :
Si = Ci . 
i
. 
i
+ 
i
. i
. Bi + Ci . Ai . Bi + i
. Ai . i
= Ci
. (i
. i
+ Ai . Bi) + i
. (i
. Bi + Ai .i)
= Ci
+ i
. (Ai
Bi)
= Ci
(Ai
Bi)
In the second table of Karnaugh, We
did not seek the optimal groupings and this, to be able to highlight the
function Ai
Bi already carried out with the sum Si.
Indeed, the 3 groupings indicated give us the equation of Ci + 1 following :
Ci + 1 =
AiBi + iBiCi
+ AiiCi
= AiBi + Ci (iBi
+ Ai)
= AiBi + Ci (Ai
Bi)
The two expressions Si and Ci + 1 which have been just calculated, we deduce the logic diagram from a full adder represented on figure 7.
The full adder is the basic circuit to carry out the sum of numbers of several bits.
There are two methods of addition of the binary numbers.
The first uses only one full adder to which one presents the of the same figures row of the numbers to be added. It is about the sum in series.
The second fact call to as many full adders than there are figures in the numbers to add. It is about the sum in parallel.
1. 5. - SOMME IN SERIES
The two numbers (here of 8 bits) to add are charged in two registers A and B as one sees it on figure 8. The result of the sum is stored in a third register S. It is also necessary to have a synchronous rocker of type D which is used to memorize the reserve of the preceding partial sum.
The 3 registers and the rocker are ordered by the same clock signal which synchronizes all the operation.
The operation of the circuit is as follows. At the beginning, the rocker must be put at 0 by activating entry CLEAR. On the other hand, the 3 registers do not need to be given to 0.
The two terms of the sum are charged in the registers A and B with a first clock pulse. The first two figures of each term (L.S.B.) are then present at the exit of the registers and thus at the entries of the adder.
Thus, one finds at the exit Si the first partial result and at the exit Ci + 1 the first reserve.
The situation is that which appears on figure 9 or one adds the two numbers of the preceding example.
The second clock pulse produces the following facts:
The first partial result is stored in the first stage of the register S.
The first reserve is memorized by the rocker.
The contents of registers A and B
shift of a stage towards the line; thus the figures of immediately higher
weight are presented at the entries of the summoner. We are then in the
situation of figure 10. The rocker from now on is symbolized by a square inside
whose its state is registered.
The data present on the entry series of the registers is of no importance. The addition proceeds in an identical way for the following figures.
After 9 clock pulses (for the loading from A and B and 8 to carry out the sum), the result of the sum is stored in the register S while the exit of the rocker indicates reserve. We are in the situation of figure 11.
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The addition taken in example has as a final reserve 0, which means that the result 1101 0110 is right.
If the rocker is with state 1, that means that the last sum gave place to a reserve of 1. One exceeds the capacity of the circuit thus, that is designated by the English term overflow which means to overflow.
There is overflow when the number which is the result of the sum has more bits than those which can be contained in the register (in our case 8).
With 8 bits, the highest number that one can represent is: 1111 11112 = 25510.
With registers with 8 bits, one can thus add the numbers ranging between 0 and 255 (expressed in decimal code), but the result of their nap should not itself exceed 255.
In the contrary case, one would obtain a result which, to be stored, would require a register of 9 bits.
By using a computer or a circuit summoner, it is always necessary to pay attention never to exceed the capacity of it. The overflow gives erroneous results. Let us suppose that one carries out the following sum :
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The last figure on the left of the result not finding a place in the register S is lost. The result which is indicated by the contents of S is 0100 0000, which is equivalent to 64 in decimal code and not 320 which is the true result.
To know if there is going beyond, it is enough to examine the state of the rocker at the end of the addition : if it is with state 0, the result is right; on the other hand, if it is with state 1, that indicates that there was a reserve of 1 during the last addition and that one exceeded the capacity of the circuit.
One can make the economy of the register S by rebouclant the exit S of the adder on the entry series of register A or B.
If one connects for example the exit S to the entry series of register A, as illustrated on figure 12, the result of the addition will appear in register A.
Indeed, with each clock pulse, the result partial of each nap is shifted in register A.
The method of the sum in series is closest in our usual way to carry out additions: one adds a figure at the same time on the basis of that with weaker weight.
However, it is rather slow because it requires as many clock pulses than there are figures to add.
For more speed, one calls upon the method of the sum in parallel where all the figures are added simultaneously.
According to the mode of calculation of reserve, one distinguishes the sum in parallel with reserve series and the sum in parallel with anticipated reserve.
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