Created it, 06/09/09
Update it, 06/09/25
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1. 6. - SOMME IN PARALLEL WITH RESERVE SERIES
Figure 13 represents a circuit of nap in parallel of 8 bits with reserve series.
We note that a circuit of nap in parallel requires as many full adders there are figures to add.
In addition, since the exit selected of an adder is connected to the entry selected of the following, the circuit summoner of figure 13 is known as with reserve series. It should be noted that the entry selected C0 of the first adder must be carried to state 0.
The method of the sum in parallel is much faster than that of the sum in series and total time to carry out the operation depends primarily on time necessary for the propagation of reserve.
Indeed, even if all the figures are added simultaneously, reserve must be propagated first with the last adder.
Thus, the result presented on the 8 exits and C8 reserve will not be exact that when this propagation is carried out.
The mechanism of the addition is as follows.
The first summoner adds the two figures A0 and B0 and generates the S0 sum and C1 reserve.
The second summoner adds the figures A1 and B1 with C1 reserve produced by the first summoner. He will not be able to add A1, B1 and C1 only when C1 reserve of the first sum is calculated by the first summoner.
A certain time thus should be waited that reserve was propagated of stage in stage so that the S7 sum and C8 reserve are established (the S0 naps in S6 will be already established). Before this time, the result contained in S is not inevitably correct.
This mechanism, similar to that met in the asynchronous meters, has the same advantage (simplicity of the circuit) and the same disadvantage (slowness).
The method of nap in parallel with propagation of reserve is however faster than that of the sum in series.
Time necessary so that a full adder calculates reserve is very short, in the case of circuits C-MOS a few tens of nanoseconds.
However, the total time of the addition is the product of this time by the number of figures to add.
It cannot then any more be neglected especially in the computers which must be able to carry out million addition a second. One has recourse to the method of nap simultaneously with anticipated reserve.
1. 7. - SOMME SIMULTANEOUSLY WITH ANTICIPATED RESERVE
To carry out the sum more quickly, should be complicated the preceding circuit.
One bases oneself on the fact that the terms of the sum are known and available before even as begins the operation of addition. One can then calculate, while anticipating, reserve for each stage independently of the preceding stages. It is a question of being able to lay out of all reserves simultaneously and in the shortest possible time.
In other words, it is necessary to calculate C1 reserve starting from the bits A0, B0 and C0, C2 reserve starting from the A0 bits, B0, C0, A1 and B1 and so on.
Figure 14 shows the synoptic one of an adder 4 bits with anticipated reserve.
To carry out the calculation of reserves in an anticipated way, it is necessary to transform the equation of reserve Ci + 1 considering previously.
Ci + 1 = Ai
iCi
+ AiBi + 
iBiCi
Since Ci + 1 is worth 1 when Ai = Bi = Ci = 1, one can add the AiBiCi terms to the expression of Ci + 1 as many time as one wants (here 2 times).
From where Ci
+ 1 = AiiCi
+ AiBiCi + AiBi + iBiCi
+ AiBiCi
= AiCi (i
+ Bi) + AiBi + BiCi (i
+ Ai)
That is to say Ci + 1 = AiCi + AiBi + BiCi
= AiBi + Ci (Ai + Bi)
Let us pose : AiBi product = pi and nap Ai + Bi = If
From where Ci + 1 = pi + CiSi
The expression of the reserve of the first stage becomes :
C1 = p0 + C0S0
and that of the second stage :
C2 = p1 + C1S1
Let us replace C1
by its computed value in
in this expression of C2
:
C2 = p1 + (Po + C0S0) S1
C2 = p1
+ poS1 + C0S0S1
In the same way :
C3 = p2 + C2S2
= p2 + (p1 + p0S1 + C0S0S1) S2
C3 = p2 +
p1S2 + p0S1S2 + C0S0S1S2
C4 = p3 + C3S3
= p3 + (p2 + p1S2 + p0S1S2 + C0S0S1S2) S3
C4 = p3
+ p2S3 + p1S2S3 + p0S1S2S3 + C0S0S1S2S3
The expressions ,,
, and
of reserves C1, C2, C3 and C4
are remarkable by the fact that they claim the same computing time and that they
thus do not take account of the reserve of the preceding stage (not of delay due
to the propagation of reserve.
To explain that, we will speak about “logical layer”.
A logical layer corresponds to the travel time of a standard elementary door AND or OR.
For example, the calculation of C1 = p0 + C0S0 requires 3 logical layers as shown in the figure 15.
Although the expressions ,
and
of reserves C2, C3 and C4
are more complex, those require for their calculation only 3
logical layers like C1.
We will now see an example of adder integrated 4 bits into anticipated reserve : 7483.
Figure 16 presents the stitching and the logic diagram of the integrated circuit 7483.
The travel times of the various entries towards the various exits of the circuit are gathered in the table of figure 17.
| Entries | Exits | Maximum time of propagation (in ns) |
| C0 | Si | 21 |
| Ai or Bi | Si | 24 |
| C0 | C4 | 16 |
| Ai or Bi | C4 | 16 |
With this integrated circuit, one adds 2 numbers of 4 bits of 24 ns maximum.
It should be noted that the integrated circuit 74LS83 which is an adder of 4 bits with reserve series carries out the same operation in 72 ns maximum, that is to say 3 times more.
If one wants to add 2 numbers of more than 4 bits, it is necessary to use several integrated adders and to connect them in cascade.
For example, figure 18 shows the setting in cascade of 2 adders 4 bits type 7483 to obtain an adder 8 bits. It is enough to connect the C4 exit of the first adder to the C0 entry of the second.
The adder obtained is only partially with anticipated reserve.
Indeed, one finds the mechanism of reserve with propagation series due to the C4 exit connected to the C0 entry.
According to the table of figure 17, the C4 exit of first 7483 is available at the end of 16 ns. In addition, like the S4 exits in S7 21 ns are available after the appearance of reserve in C0 of second 7483, we deduce from it that the result of the sum of the 2 numbers of 8 bits is available after 16 + 21 = 37 ns maximum.
Each new adder 7483 put in cascade brings an additional delay of 21 ns. Thus with 3 circuits 7483, the addition of 2 numbers of 12 bits will require 37 + 21 = 58 ns maximum.
After the adders, let us examine now the circuits comparators.
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