Created it, 06/09/09
Update it, 06/09/25
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2. - BINARY COMPARATORS
A binary comparator is a logical circuit which carries out the comparison between 2 generally noted binary numbers A and B.
It has 3 noted exits A = B, A > B and A < B which indicate the result of the comparison as follows :
If number A is equal to the number B
(A = B), the exit A
= B passes to state 1 while the
exits A > B and A
< B pass to state 0.
If number A is strictly higher than the
number B, only the exit A
> B passes to state 1.
If number A is strictly lower than the
number B, only the exit A
< B passes to state 1.
We will see how to produce using logical doors a comparator of 2 binary digits.
2. 1. - COMPARATOR OF TWO BINARY DIGITS
That is to say to compare the two binary digits A and B. Let us examine the cases where A = B, A > B and A < B.
The two numbers A and B are equal if A = B = 1 or A = B
= 0. The exit A = B must thus pass to state 1
only for these two combinations. Its equation is thus A . B + 
.
.
Number A is strictly higher than the number B only if A = 1
and B = 0. The exit A > B must thus pass to state 1
only for this combination. Its equation is thus A
Number A is strictly lower than the number B only if A = 0
and B = 1. The exit A < B must thus pass to state 1
only for this combination. Its equation B.
All these considerations are translated in the truth table of figure 19.
Let us take again the equation of
the exit A = B, AB + .
We know that AB +
+ A
+ B
= 1 bus whatever the states of A and B,
one of the four combinations is worth 1.
We deduce from it that AB +
is the logical complement of A
+ B
since the logical sum of these two expressions is 1.
Therefore, AB +
= A
+ B.
We are thus led to the logic diagram of figure 20 which provides three signals A < B, A = B and A > B starting from bits A and B.
2. 2. - ANALYSIS OF AN INTEGRATED COMPARATOR : 7485
The integrated circuit 7485 is a comparator 4 bits, i.e. it carries out the comparison of two numbers of 4 bits.
Moreover, it has 3 noted entries A = B, A > B and A < B which authorize the setting in cascade of several circuits comparators of the same type.
Thus, one can compare numbers of 8, 12, 16 bits….
The stitching of this circuit is given on figure 21, while figure 22 represents its logic diagram.
With this circuit, one compares number A made up of the bits A3, A2, A1 and A0 (A3 = MSB and A0 = LSB) with the number B made up of the bits B3, B2, B1 and B0 (B3 = MSB and B0 = LSB).
The truth table of figure 23 highlights the action of the entries A > B, A < B and A = B.
If it is wished that the exit A = B pass to
state 1 each time the two binary numbers are
equal, it is enough to carry the entry A = B
to state 1, the state of entries A
< B and A > B not having
then importance.
If it is wished that the exit A > B also
pass to state 1 if the two binary numbers
are equal, it is enough to carry the entry A > B
to state 1 and to carry the entries A
< B and A = B to state 0.
In this configuration of the state of the entries A > B, A < B and A = B, exit A > B is with state 1 when binary number A is higher than the binary number B or when these two numbers are equal. It thus indicates if A ³ B.
In the same way, while carrying entry A < B
with state 1 and entries A
> B and A = B with state 0,
the exit A < B indicates binary number A
is lower or equal to the binary number B.
By putting in series two comparators 7485, one can compare two numbers of 8 bits. It is enough to connect the exit A = B of the first comparator to the corresponding entry of the second and to make in the same way with the exits A > B and A < B. the connections to be carried out are indicated on the figure 24.
Thus, one compares formed number A of the 8 bits A7 with A0 (A7 = MSB and A0 = LSB) and numbers it B formed of the 8 bits B7 with B0 (B7 = MSB and B0 = LSB).
The first circuit compares the weak weights of A with the weak weight of B. the result of this comparison is transmitted to entries A < B, A = B and A > B of the second circuit.
This one compares the strong weights of A with the strong weights of B and, according to the result of the comparison of the weak bits of weight of A and B, indicates on its exits A > B, A = B and A < B the result of the comparison of numbers A and B.
3. - MULTIPLEXERS
In this chapter, we will examine logical circuits very much used to switch data : multiplexers.
These circuits have several inputs and only one exit.
Using one or several entries of order, one switches one of the inputs towards the exit. The exit “recopies” the selected entry.
A multiplexer can be compared with a mechanical switch. The number of the inputs of a multiplexer defines the number of ways of a multiplexer. If a multiplexer has n input, it is said that it is about a multiplexer with n ways.
The number of the entries of order is a function of the number of ways of the multiplexer. For example for a multiplexer with 4 ways, one needs 2 entries of order. Indeed, with 2 entries of order, one can form 2² = 4 distinct logical combinations to differentiate the 4 ways from the multiplexer. A multiplexer with 8 ways would require 3 entries of order since 23 = 8.
Let us examine simplest of the multiplexers, that with 2 ways.
3. 1. - MULTIPLEXER A 2 WAYS
Figure 25 gives the diagram symbolic system and the mechanical equivalent of a multiplexer to 2 ways.
According to the state of the entry of selection A, the exit S recopy either the D0 entry, or the D1 entry.
Let us suppose that for A = 0, S = D0 and that for A = 1, S = D1.
We deduce the equation from it from S following :
S = D0
+ D1A
The combinative network of figure 26 can provide the signal S.
3. 2. - ANALYSIS OF AN INTEGRATED TWO-TRACK MULTIPLEXER : 74157
The integrated circuit 74157 is a quadruple multiplexer with 2 ways at entry of common selection. The entry of validation (STROBE), also commune, forces the four exits on the level L when it is subjected to the level H.
The stitching and the logic diagram of this circuit are given on figure 27.
The truth table of figure 28 shows that the data Ai is transferred in Yi when entry SELECT is with state 0. When this entry is with state 1, it is the data Bi which is transferred in Yi.
Let us consider data A made up of the bits A1, A2, A3 and A4, the data B made up of the bits B1, B2, B3 and B4 and the data Y made up of the bits Y1, Y2, Y3 and Y4.
Under normal operation, entry STROBE is maintained to 0.
If entry SELECT is with state 0, the data Y is equal to data A.
If entry SELECT is with state 1, the data Y is equal to the data B.
A multiplexer can thus switch data made up of several bits.
3. 3. - MULTIPLEXER A FOUR WAYS
Figure 29 represents the diagram symbolic system and the mechanical equivalent of a multiplexer with 4 ways.
The multiplexer has two entries of order A and B to select one of the four entries D0, D1, D2 or D3.
In general, the selected entry carries in index the state corresponding to the combination of the entries of order. That is translated in the table of figure 30.
This table, one can extract the equation from the exit S following :
S =
.
. D0 +
. A . D1 + B .
. D2 + B . A . D3
One leads to the logic diagram of figure 31.
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