Created it, 06/09/09
Update it, 06/09/27
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2. - ELECTRONIC RAM AND DYNAMIC MEMORIES
2. 1. - DEVICES OF MEMORY
Figure 16 shows a switch used as storage element. The lever of this switch can be in two distinct positions : directed upwards or downwards.
With the first position is associated a lit lamp and with the second the same extinct lamp. Moreover, with lever in top and lit lamp, one makes correspond the logical level 1, while with low lever and extinct lamp, one makes correspond the logical level 0. Thanks to this convention, the device becomes a cell storage in two states, or binary.
The storage cell, in general, is thus a circuit or part of circuit which can store only one bit of information : 0 or 1, as represented figure 17.
The rocker is the electronic equivalent of the switch from which we come to speak. Several rockers connected in an adapted way, constitute a register, i.e. an electronic memory, either elementary but able to contain a succession of bits called sequence.
The sequences of bits, stored in the registers, can have a maximum length equal to the number of stages of each register: eight, sixteen, thirty-two bits. These sequences are called words.
One can thus define the register as being a circuit of memory able to memorize a word.
In the preceding lessons, you could examine the registers with shift or “shift register”.
We saw that there are registers with shift with entries in series or parallel and of the exits in series or parallel.
On figure 18 is represented the diagram of a register with entries and exits in parallel. Often, it is not necessary to indicate in the details how the register is designed; it is enough to draw it in the form of a whole of adjacent boxes in same number as that of the storage cells reserved for each bit.
The arrows which represent the flow of bits relating to the entries and the exits are in same number as the cells.
Sometimes, to represent the total flow of bits in entry and exit, parallel, a large single arrow is used and the symbol of the register is summarized with only one rectangle.
In this case, the number of storage cells is indicated in a number of bits (register of N bits) as you can see it on figure 19.
2. 2. - MEMORIES RAM
(RANDOM ACCESS MEMORIES) OR IN FRENCH, RANDOM ACCESS MEMORY
A memory RAM is formed many cells laid out in lines and columns, like the compartments of a rack of P.0. box (figure 20).
Each cell can be identified by using a number of column and a number of line, just like one makes it when one plays naval battle.
The term “access chance”, qualifying this type of memory, means that one can reach each box memory without respecting a preestablished order but randomly of the needs and choices.
The basic cell of an electronic memory primarily consists of a rocker equipped with an external combinative network such as it allows the recording and the reading of the data (figure 21).
By observing the graphic symbol and the logic diagram, one can see three entries and an exit : an entry for data (DIN), another to predispose the memory with the writing (W) and a third to predispose it with the reading (R) ; the exit is located by symbol DOUT. Data 0 or 1 are written in the rocker when the entry W is high, because thus their passage in memory through door A is validated. The symbol W is the initial one of “Write” which means to write.
So on the other hand, the entry W is on the level L, door A is blocked and B carries it busy. In this way, the exit Q is connected to the entry D of the rocker. So each time a clock pulse arrives, the contents of the rocker are not lost because it is re-registered through entry D.
The data present on Q is read when the entry R is at the high level, which validates the door C and makes it possible at the level available in Q to be posted on exit DOUT. The letter R is the initial one of “Read” which means lira.
The combinative network of doors which surrounds the rocker makes it possible to superimpose the operations of reading and writing even if that is not usually done, because in general, the two operations are carried out separately.
In order to differentiate the two operations, one can use a reverser such as that represented figure 22.
In this way, one obtains a terminal R / W (Read / Write) which will authorize the writing when it is to 0 and the reading when it is to 1.
Only one cell memory would present little interest. It is thus advisable to put several cells together so as to obtain larger capacities.
One could gather them one beside the other by maintaining the separate entries and exits. Thus, it would be possible to reach immediately each cell with complete freedom as have the fact for the random access memories, but that would multiply also the number of terminals of entries and exits.
In order to reduce the number of legs of the integrated circuit, one modifies the basic cell of memory as indicated figure 23.
The operation of the new circuit is simple. When E is on the level L, the output signal DOUT does not succeed in passing through the door AND, therefore one can neither read nor to write because with E on the level L, the exit of the reverser is on the level H and the entry R / W is on the level H. The order R / W is thus used to validate the reading or the writing.
From cells of this type, it is possible to carry out very large memories. On the figure 24 is represented the diagram of a memory of low capacity, of four words of two bits.
That means that there are eight gathered bits two to two in four groups and that it is possible to read two bits simultaneously.
The operation of the unit is as follows: all the entries of a column of rockers are connected together to the one of the two entries of the memory, D1 or D0, while all their exits are connected together through the OR successive ones to S1 or S0. Only the rocker validated by its entry E, can deliver at the entry of OR one 1 which, they OR being in cascade, will appear on the exit considered, S0 or S1.
The entries A1 and A0 of address select, thanks to a decoder, the line in which it is necessary to read or write.
When for example A1 and A0 are with the state 0 0, the Q0 exit of the decoder passes at the high level, which validates the two rockers of line 0 by means of the order E.
The term “addresses” used previously defines the position of the box memory inside this one; in our case, the address defines a line where a word of two bits is.
There are memories where the address defines the position only one bit ; in this case, it is necessary that the address also indicates the column ; therefore, in addition to the decoder which selects the lines, it is then necessary to have a decoder of columns. Moreover, each cell, notwithstanding an entry of validation for the line, will have an entry of validation for the column. When both are active, one will be able then to read or write.
On figure 25 is given an example of memory to 64 cells or bits, each one being accessible individually.
Here, one reads or one writes only one bit at the same time. It is thus necessary to have an address to six digits ; indeed, since there are 64 cells, 64 different combinations are necessary and are needed six digits (26 = 64) to obtain this number of combinations.
The first three bits of the address, of A0 with A2, locate the column; the three other bits of A3 with A5 indicate the line or horizontal line.
The complete address is thus formed in the following way :
This address indicates the cell located on the line 0 1 0 i.e. line n° 2 (the third on the basis of the top) and in the column 1 1 0 i.e. column 6 (the seventh on the basis of the left).
The cells are represented by a small square. For reasons of space, the various entries and the various exits are not indicated there, on the other hand they are to it figure 26.
The diagram of the memory of figure 26, although very simplified, is still rather complex ; one can easily imagine that when the storage capacity increases, the complexity of the drawing increases too!
To represent a memory, one thus uses usually synoptic diagrams even more synthetic, as that of figure 27 where all the cells are not represented with one but are not replaced by a rectangle (they are 32 lines and of 32 columns, that is to say 1 024 cells which he would have if not been necessary to represent).
By observing this diagram, one can first of all notice the presence of an additional entry CE, acronym “Enable Chip” which means “selection of case”. This entry, as we saw in certain cases, is useful when one uses several cases to carry out a memory.
One can then notice the presence of BUFFER I / O or BUFFER of input / output. As it is seen, the BUFFER is a circuit plug, here between the cells the external memories and circuits.
Letters I / O are very important because one very often especially meets them in the microprocessors, they mean INPUT / OUTPUT or Input / output.
Up to now, we saw memories at entries and exits differentiated, but in practice they are confused in order to save the pins.
The structure interns memories allows it, indeed these memories are conceived so that the entry does not disturb the exit and vice versa.
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