Rockers
with transistors |
Rock
bistable realized with doors NAND |
Rock
R.S.C. |
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Rock
of type “D” or “LATCH” |
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Created it, 06/09/09
Update it, 06/09/17
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3. - BISTABLE TRIGGER CIRCUITS
3. 1. - VARIOUS TYPES OF BISTABLE TRIGGER CIRCUITS
These are circuits whose exits have two stable states 1 or 0. They have the property to preserve these stable states after the disappearance of the logical levels which gave rise to these stable states. These circuits are regarded as storage elements able to store and provide a unit of information, i.e. a bit.
Rocker R-S or “FLIP-FLOP” is the simplest type of these new circuits. There are two types of “FLIP-FLOP”, “FLIP-FLOP R-S” and the “FLIP-FLOP with clock”.
In this theory, we will examine the asynchronous rockers, i.e. rocker R-S and its derivative, as well as the rockers D ordered by a logical level. The rockers D ordered by a clock and rockers J-K are synchronous circuits and will be examined in theory 5.
3. 2. - CROSS COUPLED ROCKERS
3. 2. 1. - COUPLED ROCKER CROSS R-S CARRIED OUT WITH NOR DOORS
a) Operation
It is about the rocker examined previously. Its diagram is indicated on figure 35.
One generally calls the exits of a
rocker, Q and 
; we will adopt however the notation 
;
Indeed,
is not always the complement of Q.
The rocker is known as SET
when Q = 1 and
= 0, it is known as RESET
when Q = 0 and
= 1.
The entries R (Reset) and S (Set) are active at the logical level H.
Let us take again the examination of this rocker by showing its operation by means of a table presenting all the successive cases which one can encounter.
This table is presented at figure 36.
Figure 36 makes it possible to follow the evolution of the circuit starting from the powering.
The states of the entries are indicated for each case as well as the corresponding states of the exits.
We see that there exists in this rocker an entry R and an entry S.
In the first case, only the state of one of the two entries of the NOR doors is known (level L). One cannot thus say which is the state of the exits, indeed, this one depends on the state of the second entry of the NOR one.
In the second case, one applies a level H to the entry R, which causes to force the first NOR one to 0. This 0 brought back on the entry higher of the second NOR force the exit of this one than 1. This exit being brought back on the lower entry of the first NOR one comes to confirm the forcing of this one to 0.
One leads thus at the first stable state of the rocker (RESET).
In the third case, R totaled 0, one notes that taking into account the former state, the rocker is maintained RESET, the first NOR one being forced to 0 by its lower entry. The exit of the second NOR one is then maintained to 1 bus its two entries are with state 0. One memorized the effect caused by R = 1 in the second case.
In the fourth case, S passes to 1 and comes to force the second NOR one to 0. By the same process due to the retro-coupling of NOR, one leads thus to the setting with 1 of the rocker or SET (second stable state).
In the fifth case, S totaled 0, one notes the maintenance of the rocker with 1.
In the sixth case, R and S are to 1 simultaneously and the two NOR doors are forced to 0.
b) Truth table
We can summarize this operation in the shape of a truth table. We will call Qn the state of the exit Q at moment n and Qn - 1 the state of the exit Q at moment n - 1, i.e. at the moment having preceded the change by state of the entries.
In a similar way, we will take
notations n
and n
- 1.
This truth table is represented on figure 37.
3. 2. 2. - ROCKERS A TRANSISTORS
Figure 38 points out the operation of transistor NPN in commutation such as you saw it in technology 1. (Synopsis digital and fundamental technology).
b) Rockers 
with transistors
In its simplest shape with discrete components, the circuit FLIP-FLOP is made up as shown in the figure 39.
Let us analyze the operation of this circuit :
When one applies 0
volt to the entry 
(
is with 5 volts), the D1
diode is crossed by a current ID1 (figure
39) and it appears a very weak tension VD1
on its terminals.
Transistor TR1
is then blocked (bases insufficiently positive so that it leads). TR1
being blocked, no current crosses it and
goes up to approximately 5 volts.
This tension is then returned
through R2 on the basis of TR2
which is saturated (running Ib2). Q
falls then to practically 0 volt. This
tension brought back through R4 on the basis
of TR1 comes to maintain the blocking of
this one, and this same if the entry
passes by again with 5 volts.
We obtain a first stable state : TR1
is blocked, TR2 is saturated. Thus, the exit
passes to 5 volts (level H)
and the exit Q passes to 0
volt (level L). The application
of one “0” on the entry
thus involves Q = 0 and
= 1. It is the state RESET
of the rocker.
So now the entry
passes to 0 volt and that
is with 5 volts (figure 40), in the same way
TR2 blocks (0 volt
on its basis) and the exit Q
passes to 5 volts (level H).
Transistor TR1 is saturated, therefore the
exit
passes on the level L.
It is the second stable state of the rocker. TR2 is blocked and TR1 is saturated.
Thus
= 0 involve Q = 1
and
= 0. It is the state SET
of the rocker.
When, as represented on figure 41,
= 0 V and
= 0 V, TR1 and TR2
are blocked because their base is maintained with approximately 0
Volt (Q =
= 5 volts is the level “H”).
The direction of the currents in the
diodes is indicated by the arrows blue and red on figure 41.
=
= 0 involve Q = 1 and
= 1.
When the two entries
and
are with state 1, the two diodes D1
and D2 are blocked and the two entries
and
do not have an influence on the assembly.
The transistors remain in the state
where they were previously. In fact thus the former states Qn
- 1 and N
- 1 are observed on Q and .
One can say that the position
=
= 1 is the position memory of the assembly.
All this can be summarized in the
truth table of figure 42, the states of the exits at moment n
being noted Qn and n
and the states at former moment n
- 1 noted Qn - 1 andn
- 1.
3. 2. 3. - CROSS
COUPLED ROCKER FLIP-FLOP REALIZED WITH DOORS NAND
The
figure 43-a represents the diagram of a rocker
with doors NAND
and the figure 43-b the symbol of a rocker .
The truth table of this rocker is represented on figure 44.
It is of course identical to that described for the rocker with elements discrete and seen in the preceding chapter.
c) Operation
Figure 45 shows the operation of
such a FLIP-FLOP. The entries
(RESET) and
(SET) are active on the level L.
d) Chronogram of a rocker
with doors NAND (figure 46).
One supposes at the beginning that
the rocker is RESET,
and
are to 1.
This chronogram can be analyzed as follows :
at moment t1 :
pass to 0 what causes to return the
rocker SET, Q
passes to 1.
at the moment t2 :
pass by again to 1, which does not have
an influence. The rocker remains SET what
wants to say that it memorizes the former action of .
at moment t3 :
pass to 0 what causes to return RESET
the rocker, Q passes to 0
and
passes to 1.
at the moment t4 :
pass by again to 1 what does not have an
effect, the rocker remains RESET what wants
to say that it memorizes the former action of .
at the moment t5 :
pass to 0 the rocker becomes SET,
Q passes to 1
and
passes to 0.
at the moment t6 :
pass to 1 the rocker remains SET.
at the moment t7 :
pass to 0 the rocker being already SET,
it remains SET.
at the moment t8 :
pass to 0,
passes to 1 but Q
remains to 1 bus
is always to 0.
at the moment t9 :
pass to 1, Q
passes to 0, the rocker is again RESET
bus
remained to 0.
at the moment t10 :
pass to 1, the rocker remains SET
what wants to say that the former action of
is memorized.
3. 3. - ROCKERS
DERIVED FROM THE CROSS COUPLED ROCKERS
3. 3. 1. ROCK R.S.C.
a) Description
It is about a rocker with doors NAND whose entries are ordered by two other doors NAND as shown in the figure 47. The entry of order “C” common to both new doors NAND makes it possible to validate the two entries R and S. Those are called R and S because these entries are active with state 1.
When C is with state 1, the entries S and R are validated and rocker R.S.C becomes a traditional rocker R-S.
When C
passes to state 0,
entries 1
and 1
pass to state 1 whatever the state of the
entries S and R.
Ainsi, the rocker
passes to the state rest. It is the position memory, i.e. the exits Q
and
remain in the state where they were before the passage of the entry C
to state 0.
If the exits Q
and
were both with state 1,
(1
= 1
= 0), rocker R.S.C goes to state 1
(Q = 1 and
= 0) or to state 0
(Q = 0 and
= 1) according
to the entry 1
or
1 which remained the last with
state 0.
b) Chronogram of a rocker R.S.C. (figure 48).
| at the moment t0 :
the rocker is RESET (Q
= 0,
= 1) |
| at moment t1 : the entry SET passes to 1 but like the entry of order C is not to 1, rocker R.S.C is in position memory (i.e. no change of state of the exits occurs). |
| at the moment t2
: S passes to 0,
there is no change of the states of Q
and of |
| at moment t3 : R passes to 1 but C is not to 1, therefore no change of state of the exits takes place. |
| at the moment t4
: R passes to 0,
there is no change of the states of Q
and of. |
| at the moment t5
: S passes to 1
whereas C is to 1,
the rocker thus becomes SET, Q
passes to 1,
passes to 0. |
| at the moment t6
: S passes to 0,
the former state of the rocker is memorized i.e. it remains SET
(Q = 1,
= 0). |
| at the moment t7 :
R passes to 1
whereas C is again to 1,
the rocker becomes RESET (Q
passes to 0 and
passes to 1). |
| at the moment t8 :
R passes to 0,
the former state of the rocker is memorized i.e. it remains RESET
(Q passes to 0,
passes to 1). |
| at the moment t9 :
S passes to 1
whereas C is always to 1,
the rocker becomes SET (Q
passes to 1,
passes to 0). |
| at the moment t10 :
S passes to 0,
there is no change of the states of Q
and of . |
c) Truth table
The truth table of figure 49 summarizes the operation of a rocker R.S.C.
It is noted that with each time C = 0, the rocker is in position memory whereas for C = 1, rocker R.S.C behaves exactly as a traditional rocker R-S.
3. 4. - ROCKER OF THE TYPE “D” OR “LATCH”
(ENGLISH BOLT)
a) Description
Rockers R-S,
and R.S.C examined previously had two entries to position the rocker
in a given state.
One R or
made it possible to put the rocker at 0
(position RESET), the other
S or
made it possible to put the rocker at
1 (position
SET).
The rocker of the type D or latch is derived from rocker R.S.C. It has, as for it, only one entry “D” to position the exits. Indeed, one places a reverser between the entry S and the entry R of rocker R.S.C.
The entry S becomes the entry D of the rocker of the type D whose diagram is represented figure 50.
The exit
becomes .
Indeed, in this rocker, the exits
Q and
are always complementary.
When
C = 1 and
D = 1, then 1
= 0 and 1
= 1. The rocker
D is thus with state
1, (Q = 1 and
= 0).
When C = 1
and D = 0, then 1
= 1 and 1
= 0. The rocker D is thus with
state 0, (Q = 0
and
= 1).
When C
passes to state 0, the rocker remains in the
state where it was before the entry C does
not pass to 0,
i.e. it is SET or RESET.
It is the position memory, the entry D does
not have from now on any more an action on the exits Q
and .
In short, when C = 1, the exit Q is at the same logical state as entry D. One says that the exit Q recopies, reproduces (or follows) the entry D (Q = D).
When C passes to state 0, there is memorizing at exit Q of the last logical state present at the exit Q thus present at entry D.
b) Chronogram of a rocker D (figure 51).
| at
moment t1 : the input D
passes to 1 but this entry is not
taken into account, indeed, it is not validated by C
(the exits Q and
do not change a state. |
| at the moment t2 : the input D totals 0 but there is still no effect on the exits bus C = 0. |
| at moment t3 :
the entry C passes to 1
but as D is to 0,
the rocker remains in position RESET
(Q = 0 and
= 1).
|
| at the moment t4 : D
passes to 1, this change of
occurring state when C = 1 is recopy
on the exits of the rocker so that this one becomes SET
(Q = 1
= 0) during time when D
is maintained to 1. |
| at the moment t5 : D
totals 0, this change of level,
intervening when C = 1, is recopy on
the exits of the rocker so that it becomes again RESET
(Q = 0 and
= 1). |
| at the moment t6 : D
passes to 1, the rocker becomes
again SET (Q
= 1 and
= 0) bus C
= 1 |
| at the moment t7 : C passes to 0, the rocker passes in position memory |
| at the moment t8 : D passes to 0 but this change of state of the entry D is not taken into account by the rocker bus C = 0. |
| at the moment t9 : C
passes to 1 and as D
is to 0, the exit Q
also passes to 0
: the rocker becomes RESET
(Q = 0 and
= 1). |
c) Truth table
The truth table summarizing operation such as it appears with the examination of the chronogram is represented figure 52.
We can deduce from this truth table that with each time C = 0, the rocker memorizes the former state of the exits.
If C = 1, the exit Q recopies the entry D : the rocker is SET for D = 1 and RESET for D = 0.
With the rocker of the type D or latch, the examination of the asynchronous circuits is completed. In theory 5, you will see the synchronous circuits and will include/understand better the difference between these two families of sequential circuits.
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