Created it, 06/09/09
Update it, 06/09/18
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In this theory, we will examine the operation of two rockers among the most used: the rocker “D” MAIN SLAVE and rocker “JK” MAIN SLAVE.
These rockers have a synchronous operation as we will see it now.
1. - SYNCHRONOUS ROCKERS
We know that the rocker D of the LATCH type makes it possible thanks to the entry of order to memorize a bit of information. This rocker D of the LATCH type functions in asynchronous mode. Indeed, when the entry of order is on the level H, the state of the exit follows the state of the entry. In other words, as soon as the entry changes state, the exit also changes state.
However, certain numerical assemblies require rockers whose exits commutate at one well defined moment. These rockers are synchronous because the taking into account of information, present on their entries, is carried out simultaneously at the time of the transition from a logical level to another from the entry from order. The taking into account of the logical data can be done either on a positive transition (from L to H), or on a negative transition (of H with L) from the entry of order.
The figure 1-a represents a positive transition (of L with H) from a logical signal while the figure 1-b represents a negative transition (of H with L) from the signal.
The passages of the high state in a low state and vice versa are not carried out in an instantaneous way that the figures 1-a and 1-b show it.
According to technology employed, the time put by a logical signal to pass from one state to the other can vary from less than one nanosecond to several hundreds of nanoseconds as we saw in the lessons of digital technology.
The figure 2-a shows a positive transition from a logical signal followed by a negative transition. One speaks then about positive impulse.
The figure 2-b represents, as for it, a negative impulse of a logical signal.
The entry of order of the synchronous rockers is called the entry of clock (in English CLOCK). Indeed, the signal applied to this entry is generally provided by an oscillator of well defined frequency. Thus possible the change of states take place at moments precise and regularly spaced in time. Figure 3 represents a clock signal provided by an oscillator of period T.
Figure 4 shows the chronogram of a synchronous rocker which memorizes the data at the time of the positive transition from the clock signal.
One realizes that the exit always does not rock with each positive transition from the entry of clock. Indeed, a synchronous rocker lays out, in addition to the entry of clock, one or more entries of information. According to the logical level of those, the rocker commutates or remains in the state where it is.
The synchronous rockers are designed starting from asynchronous rockers that one associates in the configuration MASTER SLAVE. The first of the synchronous rockers is the rocker “D” MAIN SLAVE whom we will examine now.
2. - ROCKER
“D” OF STRUCTURE MASTER SLAVE
2. 1. - CONSTITUTION AND OPERATION OF THE ROCKER “D” MAIN SLAVE
The rocker D of structure MAIN SLAVE consists of two rockers D to locking (or latch) placed one following the other. First MASTER is called, second is called SLAVE. Figure 5 shows the synoptic one of a rocker D MAIN SLAVE.
One realizes that the entry D of the rocker SLAVE is connected to MAIN the Q' exit of the rocker. That explains the denominations MASTER and SLAVE assigned to the first and the second rocker.
Indeed, the entry D of the SLAVE recopies the Q' exit of the MASTER. Any variation of the logical level at the exit of the MASTER is thus found at the entry of the SLAVE. The SLAVE is well controlled to the MASTER.
It is noticed that the entries of order of the two rockers are always located at opposite logical levels. Indeed, a reverser is located between the two entries of validation C' and C.
The entry of order which activates the entries C' and C is called ENTERED OF CLOCK (English CLOCK). Indeed, the examined rocker has a synchronous operation as you will see it.
Outside, the rocker D
MAIN SLAVE appears as a rocker having an input D
(DATED), an entry of clock (CLOCK)
and two exits complementary Q and 
.
If one adds an entry of setting to 0 (RESET) and an entry of setting to 1 (SET), one leads to the diagram of figure 6.
Let us point out the operation of a rocker D latch.
We know that if its entry of order C is carried to state 1, the exit Q recopies entry D. If one puts the entry of order C at state 0, the exit memorizes the last logical state present on the entry right before the negative transition from the entry of order.
Figure 7 points out the structure of
a rocker D latch, while figure 8 shows the
action of the entry of order C on the exits Q
and
according to entry D.
When the exit Q recopies the entry D, the rocker D latch is transparent (the logical state of the exit Q is the same one as that of the entry D). When the rocker is in position memory, it is locked (no action of the entry D on the exit Q).
These two operating modes (transparency and locking) can be symbolized by a switch which would be ordered by the entry C.
The mode “transparency” is illustrated by the figure 9-a, while the figure 9-b represents the mode “locking”.
In the mode “transparency”, the closed switch indicates well that the exit Q follows entry D.
In the mode “locking”, the open switch indicates well that the exit Q does not follow entry D. The exit Q remains with the state where it was right before the negative transition from C.
The rocker D MAIN SLAVE can be represented by the serialization of two switches ordered by the entry of clock. This representation leads to the diagrams of figures 10 and 11 according to whether the clock is with state 0 or state 1.
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It is noted that if the entry of clock of the rocker D MAIN SLAVE is carried in a stable logical state (0 or 1), the state of the entry D Indeed does not have any influence on the state of the exit Q. to go from D to Q, there is always an open switch.
We will see now that the effective commutation of the rocker can take place only at the time of the transition from the level L to the level H from the clock.
For that let us apply to the entry of clock an impulse of tension whose form is represented figure 12-a. This corresponds to reality as we saw previously, the rise and fall times of the tension not being never null.
It also should be held account owing to the fact that the reverser laid out between the two entries of order C and C' has a threshold of swing lower than that of the other logical doors of the circuit (figure 12-a).
The figure 12-b represents the logical level thus obtained on the entry of order C' of the rocker MASTER, while the figure 12-c represents the active logical signal on the rocker SLAVE.
Let us analyze the action of the entry of clock on the rocker MASTER and the rocker SLAVE :
Moment t0 at moment t1, C' = 1 and C = 0. The MASTER is transparent and the SLAVE is locked (see figure 13).
The rocker MASTER transfers the data D at Q' exit. On the other hand, the Q' data is not transferred at exit Q from the rocker SLAVE, because the latter is locked.
At moment t1, the MASTER is locked and the SLAVE remains locked since C' = 0 and C = 0 (see figure 14).
The binary data present on the entry D right before moment t1 are memorized at the Q' exit since C' passed from state 1 to state 0 at moment t1.
One thus stored the data in Q'. As the SLAVE is always blocked, this one was still not transmitted on the exit Q which remains unchanged.
Moment t1 at the moment t2, nothing changes : the data stored at moment t1 is always in Q'.
At the moment t2, the MASTER is locked and the SLAVE becomes transparent since C' = 0 and C = 1 (see figure 15).
The exit Q thus recopies the Q' entry. There is thus swing of the exit Q which thus memorizes the data present in D at moment t1.
One can also say that the data presents in D at moment t1 was transferred at exit Q to the moment t2. The transfer was thus carried out on the rising face of the clock.
Moment t2 at moment t3, there is no change since C' = 0 and C = 1.
At moment t3, the SLAVE is locked, while the MASTER is always locked. Indeed, C' = 0 and C = 0 (see figure 16. It is noted that the exits Q' and Q do not change a state.
Moment t3 at the moment t4, the MASTER and the SLAVE are always locked and the exits Q' and Q preserve their logical state.
At the moment t4, the MASTER becomes transparent since C' = 1 (see figure 17).
The new data present in D is transferred at Q' exit, but not at exit Q since the SLAVE is always locked (C = 0). It is thus noted that at the time of the negative face of the clock (of moment t3 at the moment t4), the exit Q cannot rock.
In short, the possible swing of the exit Q takes place only at the time of the rising face of the clock (transition from the level L to the level H of entry CLOCK).
The operation of a rocker D Main Slave is quite synchronous. Its role is to memorize a logical data at one precise moment. This data applied in D is taken into account at the beginning of the rising face and is transferred on the exit Q to the end from this rising face. A new transfer of the entry D towards the exit Q will take place at the time of the next face going up of the clock.
Between two successive rising faces of the clock, there is no possible change of the exit Q.
It should be noted that when the
exit Q rocks, the exit
made in the same way.
Figure 18 shows to the stages of the routing of the data in the rocker D MAIN SLAVE during the application of a clock pulse.
It should be noted that if the entry of the reverser located between the two entries of order is connected in C' and the exit connected out of C, the rocker D MAIN SLAVE thus made up takes into account the data present in D at the time of the downward face of the clock signal. It is the case of the rocker represented figure 19.
Now let us reconsider the detailed structure of a rocker D MAIN SLAVE sensitive to the rising face of the clock.
Let us replace in figure 5 each rocker D latch by the diagram of figure 7.
We end on figure 20.
The reverser placed between the
entries S and R
of the rocker SLAVE can be removed by
connecting R to'.
So the diagram of the rocker D MAIN SLAVE
becomes that of figure 21.
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2. 2. - FUNCTIONS
OF ENTRIES CLEAR AND PRESET
It remains to add to this diagram the entries of handing-over to 0 and handing-over with 1, generally called CLEAR and PRESET. Those are connected as shown in the figure 22 which thus represents the diagram of a rocker D MAIN SLAVE with the entries of handing-over with 0 and of handing-over to 1.
Let us see now how entries CLEAR and PRESET function.
2. 2. 1. - Initially, LET US CONSIDER THAT ENTRY CLOCK EAST ON THE LEVEL L
If entry CLOCK is with state 0, the SLAVE is locked.
Since the entry of order C of the slave is carried to state 0, the exits of doors NAND 5 and 6 are with state 1, whatever the state of D.
The stage of exit of the rocker D, composed of doors NAND 7 and 8, constitutes a rocker RS with doors NAND similar to that examined in the preceding theory.
The diagrams of the figures 23-a and 23-b are thus equivalent.
To put the rocker D at state 1 (Q = 1), it is necessary to position entry CLEAR with state 1 and to apply a negative impulse to entry PRESET. This one is well the entry of handing-over to 1 and it is active with state 0.
In the same way, to put the rocker at state 0 (Q = 0), it is necessary to position entry PRESET with state 1 and to apply a negative impulse to entry CLEAR. The latter is thus well the entry of handing-over to 0 and it is active also with state 0.
If one carries two entries CLEAR
and PRESET to state 0,
the exits Q and
are forced with state 1. This combination of
entries CLEAR and PRESET
is seldom used.
2. 2. 2. - IN THE SECOND TIME, LET US CONSIDER THAT ENTRY CLOCK EAST A THE STATE 1
The MASTER is locked since the entry of order C' is with state 0 and the SLAVE is transparent.
Let us position entry CLEAR
with state 1 and apply a negative impulse to
entry PRESET. As one sees it on
figure 22, this impulse will make commutate rocker RS
made up of doors NAND 3
and 4 with state 1
(Q' = 1 and '
= 0).
Since the SLAVE
is transparent (C = 1), the exits Q
and
will recopy Q' and '.
The rocker D thus will go to state 1
(Q = 1 and
= 0).
Let us position now entry PRESET
with state 1 and apply a negative impulse to
entry CLEAR. This time, the impulse will
make commutate rocker RS with state 0
(Q' = 0 and '
= 1).
Since the slave is transparent, the
exits Q and
will recopy Q' and '.
The rocker D thus will go to state 0
(Q = 0 and
= 1).
In the same way, if one carries two
entries CLEAR and PRESET
to state 0, the exits Q
and
are forced with state 1 via doors NAND
7 and 8. It
should be noted that in this case the state of the exits Q
and
is identical. One cannot speak any more then about complementary exits. This
case very is thus seldom used and certain manufacturers regard it even as
interdict.
Moreover, this state is not stable. It does not persist if entries CLEAR and PRESET return in their inactive state (i.e. 1 in our case).
In short, whatever the logical state of the entries D and CLOCK, entries CLEAR and PRESET are priority and asynchronous, which can be summarized by the truth table of figure 24. Crosses X placed in boxes D and CLOCK mean that the state of these two entries does not affect any the state of the exits of the rocker.
Two entries CLEAR and PRESET must be with state 1, i.e. inactive so that the rocker can commutate on the active face of the clock signal.
It is it should be noted that there are rockers D MAIN SLAVE whose entries CLEAR and PRESET are active with state 1. In this case, these two entries must be carried to state 0 so that the clock signal is active.
Lastly, certain rockers see their
two exits Q and
to pass to state 0 (and not 1
as in the preceding case) when two entries CLEAR
and PRESET are both active. All these
differences are explained by differences in technological constitution.
2. 3. - TRUTH
TABLE AND CHRONOGRAM
The complete operation of the rocker D MAIN examined SLAVE is summarized by the truth table of figure 25.
The symbol 
which one can see in column CLOCK of the
truth table indicates a positive transition from the clock signal.
In this table, the first three lines indicate that entries CLEAR and PRESET are priority and active on a bottom grade.
The fourth line indicates that the logical state 0 present in D is transferred to the exit Q on the rising face from the clock signal.
The fifth line indicates that the logical state 1 present in D is transferred to the exit Q on the rising face from the clock signal.
With the sixth and seventh lines, Q0
and 0
are the logical states that the exits Q and
took at the time of the last active face of the clock. These logical states Q0
and 0
could be imposed by priority entries CLEAR
and PRESET.
In other words, these two last lines
of the truth table indicate well that the exits Q
and
do not rock on a logical level of the clock signal but of course a face going up
of this signal.
Figure 26 shows to an example of chronogram of the rocker D MAIN examined SLAVE.
.gif)
At the beginning of this chronogram, entry PRESET is put at state 0, therefore it is active. The rocker is consequently with state 1. Then entry PRESET turns over to state 1. The exit Q remains positioned with state 1. Entry CLEAR receives a negative impulse which makes pass the rocker to state 0.
The second active face of the clock does not have an action on the exit Q of the rocker since it takes place when entry CLEAR is active, therefore priority. Then, entries CLEAR and PRESET become inactive since they are carried to state 1. The rocker will be able from now on to commutate only on the positive face of the clock.
With the third active face of the clock, the logical state present in D is state 1. The rocker which was with state 0 thus passes to state 1.
When the fourth positive face occurs, the entry D is with state 0. The rocker thus commutates to pass to state 0.
At the time of the fifth face going up of the clock, the rocker does not change a state since D is always with state 0.
The entry D passes to the state 1 Juste before the sixth active face of the clock. Consequently, the exit Q of the rocker passes to state 1 at the time of the sixth face going up of the clock.
2. 4. - APPLICATION
TO THE DIVIDER OF FREQUENCY BY 2
Figure 27 shows connection to be carried out to transform a rocker D MAIN SLAVE into divider of frequency by 2.
The data D
memorized at exit Q at the time of the
active face of the clock is ,
since
is connected to D. In other words, whatever
the logical state of the exit Q before the
signal of the clock, the rocker will pass in the complementary logical state
during the active face of clock. This operating mode is called in the catalogs
of manufacturers TOGGLE.
With the chronogram of figure 28,
one realizes well that the exits Q and
are at a frequency half of that of the entry of clock. The divider of frequency
by 2 is very much used in the electronic meters which will be examined later.
After the rocker D, let us examine now the rockers of the MAIN type JK SLAVE.
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