Created it, 06/09/09
Update it, 06/09/22
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4. - LOGICAL DATA TRANSMISSIONS
4. 1. - PARALLEL TRANSMISSION
Let us suppose that we want to transmit information (or data) relating to the state of four switches at a rather long distance.
The simplest idea consists in using four wire and connecting each one of them to an indicator with LED like illustrated figure 21.
This solution is certainly most convenient; moreover, it has the merit of the speed. Indeed, the state of each LED indicates the position of the corresponding switch immediately.
The transmission carried out in this way is known as parallel because four information is transmitted simultaneously on four separate wire.
The parallel transmission presents, on the other hand, the disadvantage of being expensive.
When the distance is large between the transmitter (represented here by the switches) and the receiver (represented by the LED), the wire of connections become too long and the too expensive device especially and information to be transmitted are numerous.
We thus make call generally to the transmission known as series which uses nothing any more but only one connection to transmit all information.
4. 2. - TRANSMISSION SERIES USING A REGISTER
If we take again the principle of the illustrated assembly figure 21, in a transmission series, information relating to the state of the switches is transmitted on the same line the ones after the others and either simultaneously on four distinct lines.
To carry out this, we use a register with shift parallel-series and we obtain the diagram of figure 22.
The transmission of the data is carried out in the following way :
In mode LOAD, we charge the register with information present on each entry E1, E2, E3 and E4.
Then in SHIFT mode, four clock pulses make it possible to transmit on the port serial four information after one the other.
It should be noted that on the port serial is initially transmitted information relating to the E4 entry.
Then information relating to the E3 entry, the E2 entry and the E1 entry arrives.
Figure 23 shows how varies the port serial of the register according to time and this for the example given figure 22. The entry series can be cabled indifferently on the level H or the level L.
In general, the information converted into series is not directly exploitable. Indeed, the data relating to each switch lasts only one period of clock and it thus poses a problem of storage or memorizing of the data.
It comes to the idea to use with the reception a register parallel series which with the opposite function of the register of emission.
This register parallel series is able thus to restore information in the same form that it had at the beginning.
4. 3. - TRANSMISSION SERIES USING TWO REGISTERS
Figure 24 shows how the registers of emission and reception are connected.
The port serial of the register parallel-series is connected through the line of transmission to the entry series of the register parallel series.
The clock pulses which order this last circuit can be the same ones as those of the first register.
They are then transmitted on another line. In this case, the transmission is known as synchronous.
Only one generator of clock is necessary as shown in the figure 25.
So on the other hand, the two registers are ordered by different clock signals, the transmission is known as asynchronous.
In this case, the receiving circuit has its own generator of clock as shown in the figure 26.
This one is ordered by the signal transmitted on the line. Indeed, the generator of clock of the receiving circuit must, in this case, to deliver four clock pulses synchronized with the beginning of the transmission.
The advantage of the asynchronous transmission compared to the synchronous transmission is the economy of the line which transmits the clock signal.
5. - REGISTER
A SHIFT REBOUCLÉ ON ITSELF
5. 1. - REGISTER PARALLEL - SERIES REBOUCLÉ ON ITSELF
Let us return to the register parallel-series of figure 22. With each loading, the circuit memorizes the state of the parallel entries E1, E2, E3 and E4, i.e. that of the switches.
When we apply impulses to entry CLOCK, recorded information is transmitted to the observer placed meadows of the LED.
So however there is no clock pulse, the register keeps in memory, all at least as long as it is fed, information with which he was charged.
A register can thus constitute a memory of several bits, four in the case of figure 22.
There is however a disadvantage when we carry out shifts to transmit information to the LED.
Indeed, as information shifts, that presents at the exit of the register is lost.
Thus at the end of five impulses, four information is lost.
If we do not wish to store the information or if on arrival there is a register which memorizes them, there is no problem.
On the other hand, if we wish that they are not lost, it is necessary to carry out the assembly of figure 27.
The exit of the register is connected to its entry.
Thus, information appearing at the exit and which would be lost with each shift, is brought back to the entry and is thus again memorized.
We say, in this case, that the register thus cabled carries out a rotation on the right its contents.
To illustrate this operating mode, let us suppose that the register parallel-series in question is charged with data 0011.
Let us represent each rocker by a square inside of which is registered voter are state (0 or 1).
Figure 28 shows the evolution of the contents of the register after each clock pulse.
We note that after four clock pulses, the register found the contents which it just had after the loading.
The rotation on the right of the contents of a register can also be carried out using a register series-series.
5. 2. - REGISTER SERIES - SERIES REBOUCLÉ ON ITSELF
Figure 29 shows a register series-series rebouclé on itself through a combinative network similar to that of figure 16.
This network has as a role to switch towards the entry of the register, either the entry series, or the port serial.
We find a new entry of ordering called entered of defect. When this one is on the level H, the entry series is connected to the entry of the register through the network.
The circuit behaves then like a normal register series-series: the data present at the entry series shift on the right notch with each clock pulse.
When the entry of defect is on the level L, it is on the other hand the port serial of the register which is connected to the entry of the register through the network.
The circuit thus behaves like a register with shift rebouclé on itself.
It thus carries out a rotation on the right its contents with each clock pulse.
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