Specialisation_digitale.gif

  Synchronous integrated meter : 4520  Meter-dividers by N   Meter integrated modulo 10 : 7490 
  Return to the synopsis To contact the author Low of page

Created it, 06/09/09

Update it, 06/09/23

N° Visitors  

apasrule.gif

Reception

3. - SYNCHRONOUS BINARY COUNTERS

3. 1. - DEFINITION

These are meters (discounting machines) of which all the stages (rockers) are ordered by the same clock signal.

This operating mode makes it possible to limit the duration of the periods of instability and consequently authorizes speeds of operation higher than in asynchronous mode.

3. 2. - SYNCHRONOUS MODELS OF METERS

3. 2. 1. - METER MODULO 4

This meter produced with two rockers D is represented on figure 21.

Compteur_synchrone_modulo_4.gif 

 

 

 

 

 

 

 

 

 

If you refer to the truth table of figure 11, you realize that the Q1 exit passes alternatively from the state “0” to the state “1” to each active face of the clock H.

Thus, the Q1 exit of this divider by two can constitute the least significant bit (LSB) of the meter. The first rocker D of a meter functioning in binary code besides will be always cabled out of divider by two. The Q2 exit of the second rocker of the meter modulo 4 must provide as for it, the most significant bit (MSB), it is what is represented on the figure 22.

Table_de_verite_du_compteur_synchrone_modulo_4.gif

According to the state of Q2 which is thus imposed, let us see which must be the state of the corresponding D2 entry.

If the meter is with state 0 (exits Q1 and Q2 with the state “0”), the D2 entry must be with the state “0” since with the face of clock according to, the Q2 exit must remain with the state “0”. This is symbolized by an arrow on figure 22.

When the meter is with state 1 (exit Q1 to “1” and Q2 with “0”), D2 must be with the state “1” since Q2 must pass to “1” to the active face of clock according to and so on…

From this truth table, one writes in the table of Karnaugh of figure 23.

Tableau_de_Karnaugh_du_compteur_modulo_4.gif

One can deduce some :

D2 = Q1 .Q_barre.gif2 + Q_barre.gif1 . Q2 = Q1 Symbole_du_OU_exclusif.gif Q2

It is about OR EXCLUSIVE, which appears in the assembly of figure 21.

3. 2. 2. - METERS OF MODULE HIGHER A FOUR

According to the same principle, figure 24 represents a synchronous meter of module 8 carried out with 3 rockers D.

In this assembly, there are two additional doors compared to that of figure 21.

Compteur_synchrone_modulo_8.gif

The third rocker commutates only in two cases :

     First of all, if the two exits Q1 and Q2 are at the state “1” and the Q3 exit with the state “0”. The meter indicates in this case 0112 = 310 and must pass to 1002 = 410.

      Then, it commutates when the meter is with 1112 = 710 and must pass to 0002 = 010.

To carry out these two conditions, two additional doors should be used : a door AND which receive the exits Q1 and Q2, and a door OR EXCLUSIVE receiving the Q3 exit and the exit of the door AND.

To produce a synchronous meter of module 16, it is necessary to add an additional rocker. Thus, one is led to the diagram of figure 25.

Compteur_synchrone_modulo_16.gif

Compared to the preceding assembly, this one has two additional doors : a door AND at two entries and a door OR EXCLUSIVE.

You note first of all that the diagram becomes complicated with the increase in the number of rockers. You notice that a rocker being with zero, this one passes to “1” only if all the preceding rockers are to “1”. This explains the use of the doors AND.

It would be possible to add new rockers in order to increase the capacity of the meter. Nevertheless, the diagram would quickly become very complex, therefore it will be preferable to use the meters in integrated circuits.

It is possible to calculate the speed of operation of a synchronous meter of module 16.

If we take again the same values as in the chapter 2. 3. , namely q » 100 ns and if one always holds 100 ns to take contained meter, one lead to a limiting frequency:

Frequence_maximum_du_compteur_synchrone.gif

We can note that during the 100 ns reserved for the taking away, the combinative network formed by the doors AND and OR EXCLUSIVE A time to stabilize itself.

Actually, the synchronous integrated meters authorize speeds of operation much higher than that calculated here.

HIGH OF PAGE 3. 2. 3. - A SYNCHRONOUS INTEGRATED METER : 4520

The integrated circuit HEF 4520 B is carried out in technology MOS.

It includes/understands a double synchronous binary counter 4 bits. Its synoptic and its stitching are given to figure 26 and the logic diagram of one meter on figure 27.

Brochage_du_CI_HEF_4520B.gif

Each meter includes/understands an entry of active clock on a face going up (CP0) and an entry of active clock on a face going down (CP_barre.gif1).

Schema_logique_d_un_compteur_CI_HEF_4520_B.gif

There is an entry of restoring asynchronous MR. for each meter. It is priority and active at the high level. It is possible to use one of the two entries of clock as entered of validation while the other receives the clock signal.

HIGH OF PAGE 4. - METERS - DIVIDERS BY n

4. 1. - THE DIAGRAM OF THE STATES

The state of a meter is the particular combination formed by the whole of the exits of this meter. A meter modulo 2 has two states. Its single exit is either with the state “0”, or with the state “1”. A meter modulo 4 has 4 states. Its two exits can carry out 4 different combinations (00, 01, 10, 11).

The diagram of the states of a meter makes it possible to represent the whole of the states which this meter can take. Figure 28 represents the diagram of the states of a meter modulo 4.

Diagramme_des_etats_d_un_compteur_modulo_4.gif

In this diagram, each state is represented by a decimal number in a circle. The arrows represent the direction of “course” of the meter.

The diagram of the states can also be represented as indicated in figure 29.

Diagramme_des_etats_d_un_compteur_modulo_8.gif

Generally, it is said that a meter has n states, or although it is about a divider by n. One speaks then about meter-divider by n.

To each impulse on the entry of clock the meter passes from a state to the following by respecting the order given by the diagram of the states.

4. 2. - METER NOT USING the BINARY CODE

Until now, you saw meters using the binary code, but there are also meters using of other codes.

It is the case of the meters of Johnson whose example will be presented to you in the following theory, because these meters use a circuit of decoding.

Figure 30 presents the table of the states of such a meter at 5 stages. It is about the circuit of counting of the integrated circuit HEF 4017 B carried out in technology MOS.

Table_des_ιtats_d_un_compteur_de_Johnson_a_5_etages.gif

These five exits Q1, Q2, Q3, Q4 and Q5 are exits of the rockers, interns to the integrated circuit, and consequently, are not accessible.

This meter uses the principle of a register with shift rebouclι on itself.

Indeed, at the time of the first clock pulse, the Q1 exit passes to the state “1” then, this state “1” shifts of Q1 towards Q5. Once the Q5 exit passed to the state “1”, the Q1 exit passes by again with the state “0” with the active face of clock according to. On the whole, this meter has ten states and can enter nine impulses.

4. 3. - METER A MODULATES VARIABLE

Until now, you saw meters whose module is a power of 2 (2, 4, 8, 16,…). However, it can be necessary to have meters of which the module is an unspecified integer (3, 5, 7, 9, 10,…).

It is then necessary to modify the circuits of counting seen until now. Figure 31 presents a synchronous meter modulo 3 carried out with two rockers D.

Compteur_synchrone_modulo_3.gif

The chronogram of operation and the diagram of the states are represented on figure 32.

Chronogramme_et_diagramme_des_etats.gif

Let us suppose that the meter is with state 0. Q1 and Q2 are with the state “0”, therefore Q_barre.gif1 and Q_barre.gif2 is with the state “1” and D1 is with the state “1”.

At moment t1, the meter passes to state 1 (Q1 = “1” and Q2 = “0”). At the moment t2, the meter passes to state 2 (Q1 = “0” and Q2 = “1”).

At this time there, D1 = “0” and not “1” like in the case of the meter modulo 4. Thus with t3, the meter “is forced” with state 0 and does not pass by state 3.

At the powering, it can happen that the meter is positioned with state 3. In this case, it passes by again with state 2 with the first rising face of clock and, consequently, it remains in the ring of the three states (0, 1 and 2) without never returning to state 3.

This meter is a meter with incomplete cycle and synchronous reaction. Indeed, the cycle is incomplete since two rockers D allow 22 = 4 different states and that one uses 3 of them in this case.

In addition, the reaction is synchronous since the door AND makes it possible to decode state 2 (102 = 210) and that the restoring is carried out with the active face of clock.

There are also meters with incomplete cycle with asynchronous reaction.

If the meter must total 0 after the state N, it is enough to decode the state N + 1, which makes it possible to give the meter to 0 while acting on asynchronous entry CLEAR. An example is given to you hereafter.

4. 4. - SYNCHRONOUS AND ASYNCHRONOUS DECADES

The decades are meters having 10 stable states. These are meters that one usually meets. Indeed, they make it possible to materialize the decimal notation directly.

We will see two models of decades carried out with discrete rockers and an integrated meter.

4. 4. 1. - ONE DECADE ASYNCHRONOUS

Its diagram is given on figure 33.

Compteur_asynchrone_modulo_10_realise_avec_des_bascules_D.gif

The chronogram of figure 34 makes it possible to include/understand operation of it.

Chronogramme_du_compteur_asynchrone_modulo_10.gif

This assembly is an example of meter with incomplete cycle with asynchronous reaction.

Indeed, in this case, it is the state 1010 (10102) which is decoded using the door AND and which authorizes the master clear of the four rockers.

Nevertheless, this assembly poses a certain number of problems of operation :

      First of all, it is necessary that T is higher than t1 and t2, therefore that the restoring of the rockers is very fast (T is the duration of the reset pulse at the exit of the door AND).

Indeed, if the reset pulse passes by again with state 0 before one of the rockers (here the second and the fourth) did not pass by again to zero, the latter will remain with the state “1”.

If, for example, period t1 is very short and t2 very long and that in addition the travel time through the door AND is also very short, the Q4 exit can remain with the state “1”, therefore the meter will pass from the state “9” to the state “8”, then will pass by again with the state “9” and so on…

Practically, it is necessary to introduce delays by cells RC placed at the entry of AND as indicated in figure 35.

Cellule_RC_sur_la_porte_ET.gif

Then, the door AND can detect the above-mentioned transitory states (paragraph 2. 3.) and to return the operation of the unforeseeable unit.

In general, it will thus be necessary to be very attentive with the choices of the components and the realization of this type of circuit.

4. 4. 2. - ONE DECADE SYNCHRONOUS

The diagram of figure 36 is that one decade synchronous carried out with rockers JK of the type 7472.

Une_decade_synchrone_de_type_7472.gif

Let us recall that the three entries J, as well as the three entries K end on a door AND. Therefore the entries not used are connected to “1”.

With this synchronous assembly, the problems encountered with the asynchronous decade do not exist any more.

HIGH OF PAGE 4. 4. 3. - A METER INTEGRATED MODULO 10 : 7490

It is a meter very much used. Its diagram is given on figure 37.

Schema_du_compteur_integre_TTL_7490.gif

This meter is produced in technology TTL. Its stitching is given on figure 38. Symbol “NC” means “off-line”.

Brochage_du_compteur_7490.gif

This circuit comprises two sections. A section divider by 2 and one section divider by 5.

It is possible either to use them separately, or to join together them together to obtain a meter BCD modulo 10 or of a divider by 10.

The first section divider by 2 is consisted the first rocker JK whose entry of clock is noted “INPUT A” and the exit “Q0”. The entries J and K not cabled on the diagram all are attached at the logical level H.

The second section comprises three following rockers JK. The entry of clock is noted “INPUT B” and the three exits are Q1, Q2 and Q3. This third Q3 exit delivers a signal divided by 5 compared to the clock signal applied to the entry “INPUT B”.

This meter modulo 5 uses the binary code.

To obtain a meter modulo 10 codes some BCD, it is enough to connect the Q0 exit to the entry INPUT B. the Q0 exit which divides by two the frequency of clock orders itself the section divider by 5. It is thus possible to collect a signal at Q3 exit whose frequency is the 1 / 10θme of that of the clock.

The truth table of figure 39 makes it possible to specify the general operation of this meter.

Table_de_verite_du_compteur_7490.gif 

The two entries R9 (1) and R9 (2) allow prιpositionner the meter state 9. These entries have priority on the entries of restoring (R0 (1) and R0 (2)).

SD is the entry of setting to “1” and RD is the entry of setting to “0”.

There is a second possibility of connecting the two sections. It is to connect the Q3 exit to the entry “INPUT A”. This makes it possible to collect a signal whose frequency is worth always the 1 / 10θme of that of the clock but this time, the signal has a cyclic report/ratio equal to 1 / 2. This appears on figure 40.

Signaux_issus_des_sorties_Q3_et_Q0.gif

On the other hand, with this connection, the four exits do not use code BCD. The meter obtained account as follows: 0, 1, 2, 3, 4, 8, 9, A, B, C.

Click here for the following lesson or in the synopsis envisaged to this end. Haut de page High of page
Preceding page Following page

 

     

Daniel