Functions
NAND, NOR, OR Exclusive in N-MOS |
Basic
device in Technology C-MOS |
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Created it, 06/03/17
Update it, 06/03/26
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In this theory, we will examine the logical family with transistors MOS. Other logical families will be evoked. Lastly, we will approach the manufacture of the integrated circuits.
1. - SWITCHING FUNCTIONS A FIELD-EFFECT TRANSISTORS
The field-effect transistors to junction are not used to materialize the switching functions.
On the other hand, the field-effect transistors to insulated grid, TEC-MOS, are them, very much used. They allowed the crossing of an additional stage in the field of the integration of the functions.
This is due, partly, with the relative facility with which one can carry them out compared to the bipolar transistor and their low fuel consumption (thus weak dissipation from where weak rise in temperature per mm² of integrated circuit).
They can replace ohmic resistances, which is very important on the level of integration, because they occupy much place and more especially as their values are important.
We know that there is MOS with channel N, channel P, enrichment or impoverishment (still called: with déplétion or constriction).
If one wants to preserve a certain compatibility between technology TTL and MOS, it is imperative to preserve the same polarity for the food, which can be easily implemented with the channel N. In addition, the enrichment mode is simpler to realize.
It thus will be question initially of MOS channel N to enrichment. Thereafter, we will see that there is another way of proceeding with what the specialists call technology COS - MOS or C-MOS (complementary - symétry - MOS = transistor MOS with complementary symmetry) which uses the channel N and the P channel.
1. 1. - THE BASIC DEVICE IN TECHNOLOGY N - MOS
The figure 1-a represents the basic device. It is a NOT-circuit as its truth table proves it.
In the absence of Ve tension on its entry ; either Ve = bottom grade or state 0, the transistor is blocked and Vs (output voltage) is equal to + VDD or the high level or state 1.
In the contrary case, Ve = + VDD high level or state 1. The transistor is conductive and Vs is on the bottom grade or state 0.
The figure 1-b presents its network of characteristics and its line of load of slope - (1 / Rd) (Rd = resistance of drain).
The figure 1-c illustrates the characteristic of transfer of this assembly. Tension VDS represents the output voltage Vs. tension VGS is the tension of Ve entry.
When a tension of entry is applied,
the output voltage remains stable and at the high level, until one reaches
tension VT, or tension of threshold for
which the transistor starts to lead, then if one continues to increase the
tension of entry, VS decrease according to
the curve 
until the bottom grade or state 0.
One realizes that the stronger
resistance RD is, the more one reaches the
bottom grade quickly (curve 
).
On the other hand, if RD
is too weak, the bottom grade is obtained for a tension of Ve
entry higher than tension VDD (curve 
).
It is thus rather towards a large RD that one will be directed, but we know that the realization, on integrated circuit, of a resistance of strong value poses a serious problem.
The figure 2-a brings a solution to this shelf.
If one joins together the grid with the drain of a transistor N-MOS (N for channel N) to enrichment and that one raises ID according to VDS, one obtains the curve of the figure 2-b.
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Practically, this one is a line which does not pass by the origin of the axes.
This line roughly represents the curve characteristic of a resistance.
The shift on the axis of tensions VDS can be compared to a tension in series with this resistance, schematized on figure 2.-c.
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The transistor, assembled kind, thus behaves like a resistance in series with a generator of tension VT.
Until VDS = VT, current ID is extremely weak, beyond, it grows almost linearly with VDS (see figure 2-b).
We come to the figure 3-a, on which we replaced RD by T2.
The substrate of T2 is joined together with the potential of reference 0 bus it must always be with the most negative potential of the assembly.
On the figure 3-b, we find network ID function of VDS of transistor T1 and the line of load whose slope is the reverse of the resistance obtained with T2. By construction, one makes so that this resistance is rather strong in order to as much as possible reduce the time of transition between the two states from T1.
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The figure 3-c represents the characteristic of transfer of this assembly. It should be noted that the output voltage in a high state is not equal any more to + VDD but with :
VS = + VDD - VT
Indeed, figure 3-d, we note :
VDD = VT + VDS (T1)
VDS (T1) = VDD - VT
By neglecting the tension obtained by the product of R and the leakage current of T1 (this current is extremely weak).
The figure 3-a is the final version of the basic device, the reverser with transistor N-MOS with enrichment.
1. 1. 1. - FUNCTION
NAND
Figure 4 represents the NAND in technology N-MOS and its truth table.
1. 1. 2. - THE NOR FUNCTION
It is schematized on figure 5 with the truth table which is referred to it.
1. 1. 3. - THE FUNCTION OR EXCLUSIVE
Figure 6 shows the artifice used for the construction of one OR Exclusive.
One uses an NOR function made up around T1 and T2 and thus the load is TA (identical on NOR figure 5), a function NAND made up of T4 and T5 and whose load is TB (identical to the NAND of figure 4).
Transistor T3 is assembled out of reverser. At its exit, the signal is thus a + b.
The exit of this transistor is connected to the exit of operator NAND.
These two exits thus fulfill the function AND “cable length”.
Indeed, if one of the exits a
+ b or 
passes to state 0, the exit S
passes to state 0.
Thus S = (a
+ b) .
Let us apply the property of the distributivity of the logical product compared to the logical sum:
S = a .
+ b .
Let us replace
by +
(Theorem of Morgan).
S = a (
+ )
+ b (
+ )
= a
+ a
+ b
+ b
= a
+ b
(since a
= b
= 0) = 
Thus, the assembly of figure 6 which fulfills the function OR Exclusive, uses in all and for only seven transistors MOS. In technology TTL, this function would have claimed the use of four doors NAND, that is to say sixteen transistors. This leads us to say that technology MOS is of a relatively weak cost price (the least expensive of all).
The consumption is lower than for the TTL, but remains sufficiently high to limit the level of integration.
In addition, the speed (i.e. the maximum frequency of operation) of these devices is rather low.
Immunity with the noise is better than with the TTL.
Since it is always necessary to evolve/move, the following stage is very traced. Why not use complementary transistors MOS ?
Such will be the subject of the following chapter.
1. 2. - THE BASIC DEVICE IN TECHNOLOGY
C-MOS
The figure 7-a corresponds to the basic device. It is about a transistor T2 channel P assembled in series with a transistor T1 channel N. the two grids is joined together and forms the single order.
The drains are connected electrically to the exit. (Return to the 3rd lesson)
The source and the substrate of T2 (channel P) are connected to + VDD whereas the corresponding electrodes of T1 (channel N) are connected to the potential of reference (which one calls, in this case, Vss).
Operation is illustrated appears 7-b. When the tension of Ve entry is at the high level (state 1), transistor T1 is conductive whereas T2 is blocked.
The exit S is on the bottom grade (state 0). The consumption of the assembly in this state is practically null.
When the entry is carried on the bottom grade (state 0), transistor T1 is blocked and T2 becomes conducting (tension VGS of T2 being negative).
The exit S is at the high level (state 1). Consumption in this new state is still practically null.
Once again, the basic device is an assembly reverser.
If consumption, in the two static states of the assembly, is null, it is not the same at the time of the transition which separates these states. During a short moment, the two transistors are simultaneously conductive thus creating a call of current. In complex logical systems, if the entry often changes state, the call of current much more often appears and to operation, to a raised frequency, corresponds a quasi permanent consumption thus important.
1. 3. - CORE OPERATORS IN C-MOS
They are presented on figure 8, with their truth tables.
They are the circuits fulfilling the NOR function and function NAND.
Each pair of transistors is located by T1 and T2 so that the analogy is easier to you compared to the basic assembly of the figure 7-a.
This technology, in spite of its manufacturing cost higher than for the N-MOS, is more widespread than the latter.
The speed of operation is less low than for the TTL, which is much more expensive, however, it tends to be very strongly established compared to this one.
Its immunity with the noise, definitely better, indicates it for the industrial assemblies in disturbed environment.
The number of integrated functions is from now on comparable with that of the TTL which was, until now, definitely at the head.
Lastly, a new series, carried out under name 74 C…, is the exact counterpart, with regard to the case, stitching and the tensions of series TTL, it is thus directly interchangeable with the latter.
In the industrial systems, it seems that currently, these two technologies dominate compared to the others.
Other favors C-MOS, its beach of supply voltage: of 3 volts to 18 volts.
Its travel time is a function of the voltage supply and it decreases with the increase in the latter. To compare with the TTL, these times will be given with a food of 5 volts.
tPHL = 35 ns
tPLH = 100 ns
Static immunity with the noise, for the same supply voltage, is 1,5 minimum volt.
The disadvantage, compared to bipolar technologies, is its brittleness compared to the static heads, due to the great impedance of the entries.
Protective circuits, carried out with diodes, are placed on all the entries between those and the two poles of food (figure 9 represents the protective circuit).
In spite of these measurements, it is necessary, during their handling, to take a certain number of precautions (soldering iron low-tension, to avoid synthetic matter clothing and the carpets or fitteds carpet).
It is even advised to connect the wrists of the manipulators, using bracelets, with a good earth electrode.
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